Intel Advanced Packaging for Bigger AI Chips

This week in IEEE Electronic Components Conference and Packaging Technologyand Intel The unveiling of a new development Fill chip Technology that will allow the largest Processor For artificial intelligence.

With the slowdown of Moore, the applicants of the applicants Graphics processing units Other data center chips were forced to add more silicon area to their products to keep pace with the unavoidable height of computing needs in artificial intelligence. But the maximum size of a single silicone slice is fixed at about 800 millimeters (with One exception) Therefore, they had to resort to Advanced packaging techniques Merging multiple pieces of silicone in a way that allows them to behave like one slice.

Three innovations Intel ECTC’s disclosure to treat restrictions in the amount of silicone that you can press in one package and the size of this package. It includes improvements to the technology that INTEL uses to connect the adjacent Silicon together, which is a more accurate way to connect silicone to the beam pillar, and a system to expand the size of a critical part of the package that removes heat. Together, the technologies allow me to integrate more than 10,000 square millimeters of silicone into a package that can exceed 21,000 mm²A huge area of ​​four and a half size Credit cards.

Emib gets a three -dimensional upgrade

One of the restrictions imposed on the amount of silicone in one package is related to the connection of a large number of silicone on its edges. The use of the organic polymer package to connect silicone is the most expensive option, but the silicone substrate allows you to make more intense connections on these edges.

Intel, which was presented more than five years ago, is to include a small piece of silicone in the organic package below the edges adjacent to the silicon. This shrapnel from silicon, called EMIB, is engraved with a fine Interconnection Which increases the intensity of communications to exceed what the organic substrate can deal with.

In ECTC, Intel unveiled the latest development on EMIB technology, called EMIB-T. In addition to the usual horizontal interconnection, EMIB-T provides relatively thick copper contacts called Through Silicon ViasOr tsvs. TSVS allows energy from the circuit board below to connect directly to the chips above instead of having to guidance around the EMIB, which reduces the lost energy on a longer journey. In addition, EMIB-T has a copper network that works as a ground plane to reduce the energy that is delivered due to cores and other circles that suddenly intensify the work of work.

“It seems simple, but this is a technique that brings a lot of ability to us,” says Intel’s Vice President of Packaging Technology in Intel. However, other technologies described by Intel, the customer can connect the bonus silicone to more than 12 Silicone dies full-size -10,000 square millimeters of silicone-in one package using 38 or more of EMIB-T bridge.

Thermal control

Another Intel technique reported in ECTC, which helps to increase the size of packages is low -degree thermal interconnection. It is a type of technology used today to connect a silicone that dies on organic pillars. Broats of welding are placed across the micrometer on the substrate, where they will connect to silicone death. Then death is heated and pressed on the microbe, melting it and connecting the package to the beam to the silicon.

Since silicon and scandalists are expanding at different rates when heated, engineers must limit the distance of participation or the stadium. In addition, the difference in expansion makes it difficult to make very large pillars full of a lot of silicone death, a trend in which artificial intelligence treatments should go.

Manipali says that new Intel technology makes the thermal expansion matching more predictable and manageable. The result is that very large pillars can be filled with death. Instead, the same technology can be used to increase the density of the connections to format to about one every 25 micry.

Summary heat spread

These larger silicone gatherings will generate more heat than today’s systems. Therefore, it is very important not to hinder the heat track from silicone. An integrated metal piece called the heat distributor is the key to that, but make one large enough for these large beams difficult. The substrate can distort the package and the mineral heat escape may not remain completely flat; Therefore, it may not touch the hot death tops from which the heat is supposed to absorb. The Intel solution was to collect an integrated heat set in parts instead of one piece. This allowed her to add additional graphic components among other things to keep everything in a flat place and in place.

“Maintaining it at high temperatures is a great benefit for reliability and return,” says Manibali.

Intel says that the technologies are still in the research and development phase and will not comment on when these technologies will appear commercially. However, they are likely to reach the next few years for Intel foundry To compete with The planned packaging expanded in TSMC.